25/06 satish kumar
associate at amisign

Views:102 Applications:8 Rec. Actions:Recruiter Actions:2

AmiSign Technologies - Physical Design Engineer - Primetime/DRC/LVS (15-20 yrs)

Bangalore Job Code: 460011

Responsibilities :

- Develop and implement methodology for fullchip static timing analysis for high end server class processor chips in finfet process

- Generate and review hierarchical timing constraints and exceptions for functional and test mode operation

- Drive fullchip timing convergence across multiple voltage domains

Requirements :

- Expertise in Static Timing Analysis tools (Primetime, Tempus) particularly constraints and exceptions

- Prior experience converging large high-speed hierarchical designs

- Experience with constraint-checking tools a plus

- Familiar with Spice, RC extraction and correlation, xtalk analysis, DRC/LVS and tapeout issues.

- Proficiency using Tcl, Perl, shell scripting

Other Skills :

- Demonstrates good analysis and problem-solving skills.

- Inherent sense of urgency and accountability.

- Ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.

- Ability to multi-task in a fast-paced environment.

Education : MSEE 8+ years- experience or BSEE with 10+ years related experience

Women-friendly workplace:

Maternity and Paternity Benefits

Add a note
Something suspicious? Report this job posting.