Aashi Technologies - RTL Design Engineer - ASIC/Verilog (4-6 yrs)
Please find the below JD of RTL Design Engineer
Profile- RTL Design Engineer
Yrs of exp : 3 - 8
Location : Bangalore
Skills : Worked on RTL desing,
- Good knowledge in Verilog Simulation,
- Worked in RTL with ASIC Flow,
- Ability to provide constraints for synthesis and understand P&R flow.
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