IT Recruiter at Infinity HR Consulting Pvt. Ltd.
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STA Engineer - Synthesis/DFT/TCL (1-2 yrs)
Super critical opening for STA Engineer
Requisition : STA (Static Timing Analysis) Engineer
Experience Level : 1 TO 2 years experience as STA engineer
- Competent in basics of timing analysis.
- Can perform a full block level timing analysis.
- Can perform a full IP level synthesis and timing analysis.
- Able to setup Full chip Level Timing Constraint
- Can perform timing fixes on the netlist
- Knowledgeable on mode analysis, case analysis and On Chip Variation(OCV) timing analysis.
- Competent to perform timing analysis with designs having multiple clocks
- knowledgeable to understand the various clock synchronization schemes for multi-clock design.
- Experience on multimillion Gate and complex design with multiple clocks and power domains with minimal supervision.
- timing closure flow with hands-on experience in formal equivalence, placement, optimization, low power checks, clock tree
- Experience in developing and supporting fully automated STA scripts/flows
- Knowledge of commonly used clocking, low power schemes, DFT techniques are added advantage.
- Good control over scripting languages like PERL/TCL is MUST.
Optional Experience : - Basic knowledge of networking SoCs as per our Product Requirement