07/01 Sushmita
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SerDes Design/Verification Engineer - VLSI/Verilog (3-8 yrs)

Bangalore Job Code: 200597

Opening for Bangalore based Organization

Member Technical Staff, SerDes Design/verification

Qualification: BE/B.Tech in VLSI/ECE.

- 3+ years of experience in verification of analog mixed signal blocks. Should have working knowledge of SerDes blocks.

- should have exposure to verilog coding and setting up of mixed signal test bench. Working knowledge of protocols like USB, PCIE is desired.

Tools: cadence AMS tools and proficiency in Verilog, veilogA and VAMS languages

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