21/02 Sushmita
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DFT Design Engineer - SCAN/MBIST (3-10 yrs)

Delhi/NCR Job Code: 211243

Designation : Senior/Staff Design Engineer

Job Description :

- The selected candidate will be an individual contributor who is responsible for SCAN, MBIST and JTAG implementation, verification, vector generation and ATE post-silicon debug for complex 40nm and 28nm Transport products.

Experience Level : 6-13 years of relevant DFT experience

Responsibilities :

- Responsible for JTAG implementation and verification.

- Responsible for MBIST implementation and verification.

- Responsible for SCAN insertion and DRC analysis/debug.

- Responsible for achieving high SCAN coverage and low DPPM.

- Responsible for SCAN, MBIST and JTAG gate-level simulations.

- Responsible for ATPG vector generation and ATE debug.

- Contribute to overall DFT methodology/tooling for 28nm flow.

- Contribute to SoC DFT SCAN, MBIST and JTAG architecture.

- Contribute to SCAN, MBIST and JTAG timing constraints/analysis.

Requirements :

- Strong understanding of DFT methodologies and tooling.

- DFT experience on SoC's with multiple scan chains and clocks.

- SCAN chain implementation at chip and block level.

- MBIST implementation at chip and block level.

- JTAG implementation at chip level.

- Gate simulation setup and debug.

Optional Experience :

- Test mode timing constraint development and analysis is a plus.

- Understanding of test compression and ATE debug is a plus.

- DFT architecture experience is a plus.

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