Lead - Talent Acquisition at Ashtopus Consulting
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Design & Verification Engineer - RTL Design (5-10 yrs)
RTL Design :
Candidates with a degree in Electrical Engineering with 5+ years of experience in Micro Architecture, RTL Development and debugging. Ideal candidate will have the skills in PCIe Link layer development and good understanding of the PCIe protocol. Minimum skills expected: Verilog, System Verilog, Understanding of OVM Methodologies. Additional valuable skills: PCIe or Ethernet development experience.
Design Verification :
- Candidates with a degree in Electrical Engineering or Computer Science with 5+ years of design verification experience and recent work experience in System Verilog, OVM/UVM methodologies.
- Should be well versed with test plan development, behavioral model development, test case development, code coverage enhancement and scripting.
FPGA Design :
- 5+ years of experience with FPGA development including RTL development, Simulations, Place and Route as well as debugging. Experience in Synopsys HAP platform is a plus but not required.