Recruiter at Net Creative Mind
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ASIC Verifications Engineer - System Verilog (5-8 yrs)
We have an urgent opening for ASIC Verification Engineer (Contractual Position) with one of our client in Hyderabad location.
Job Location : Hyderabad
Designation : ASIC Verification Engineer
Exp : 5 - 8 yrs
Salary : Not disclosed by recruiter
Job Description :
- Good Experience in System Verilog OVM, UVM, VMM.
- Plus Experience in memory verification using DDR
- Good Gate level sims setup experience.
- Must have executed at-least 1 SoC project.
- Design Verification Failure Analysis exposure
This job opening was posted long time back. It may not be active. Nor was it removed by the recruiter. Please use your discretion.