Senior Talent Acquisition Specialist at eInfochips
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ASIC Verification Engineer - UVM/OVM/VVM (3-9 yrs)
Position: Verification Engineer
Job Location: Ahmedabad
Experience: 3 to 8 Years
Position: Full Time
- He/She will be responsible to execute development and verification activities individually/in team with/without guidance.
- He/She will be involved in developing Testbench for the Block / Cluster, Testcases, Tesplans and Functional and Code coverage closure activities and reviews of documents and code.
- He/She will be individually responsible for successful delivery to clients for given tasks/module of Testbench/Testcases.
- He/She will responsible for the Client Support activities which conference call on reviews and Bug closure.
- At-least 1 year of experience in System Verilog with OVM/UVM/VMM/Test Harness.
- Experience in developing test and coverage plan and Verification environment.
- Knowledge of industry standard protocols like Ethernet, PCIe, MIPI, AXI-AHB Bus etc. will be added advantage.
Education: Bachelor's degree in Engineering.